1. Field of the Invention
The present invention relates to analog-to-digital ("A/D") converters and, more particularly, to successive approximation type A/D converters.
2. Description of Related Art
Generally, a successive approximation type A/D converter includes means for sampling an analog voltage input, means for suppling a successive approximation control digital output, means for comparing analog voltages, and means for successively determining values of bits of an A/D conversion output. In operation, a typical successive approximation type A/D converter samples an analog voltage input, supplies a successive approximation control digital output from a successive approximation type control circuit to a local digital-to-analog ("D/A") converter to cause the D/A converter to generate a local analog voltage, compares the sampled and held analog voltage with the local analog voltage, and successively determines the value of each bit of an A/D conversion output on the basis of the relationship in magnitude between the compared voltages. By doing the foregoing, a successive approximation type A/D converter obtains an A/D conversion output having a plurality of bits from the successive approximation type control circuit.
A more detailed description of an algorithmic A/D converter is set forth in the background section of U.S. Pat. No. 5,017,920 to French. The converter described therein includes a signal input line or system input terminal which receives an analog signal. The analog input signal is sampled in sample and hold circuitry. A switch connects the output terminal of the sample and hold circuit to an input terminal of a comparator and to the positive input terminal of a subtractor.
In the example presented in U.S. Pat. No. 5,017,920, the input analog signal is assumed to have a maximum value of Vm. The comparator compares the input signal sample with a threshold voltage Vm/2. If the signal exceeds the threshold voltage, the comparator outputs a one (1).
A switch control connected to the output of the comparator controls the value of voltage applied to the negative input terminal of the subtractor. The subtractor removes a voltage or value corresponding to the threshold exceeded from-the input analog signal.
French's switch control applies the appropriate voltage to the negative input terminal of the subtractor. If the comparator outputs a one (1), indicating that the threshold Vm/2 has been exceeded, the switch control applies the voltage Vm/2 to the negative input terminal of the subtractor. If the comparator outputs a zero (0), indicating that the threshold Vm/2 has not been exceeded, the switch control applies zero (0) voltage to the negative input terminal of the subtractor, so that the output of the subtractor has the same applitude as the input. Thus, the most significant bit of the digital representation of the magnitude of the analog signal received on the system input terminal is generated on the comparator output terminal.
The next most significant bit is generated by multiplying the output of the subtractor by two in a multiplier, and repeating the comparison step described above.
French also teaches that his switch closes the connection between a sample and hold circuit connected to the output terminal of the multiplier and the input of the comparator. The doubled output of the subtractor can then be compared with the threshold voltage Vm/2. The output of the comparator a binary one (1) if the threshold voltage is exceeded, a binary zero (0) if the threshold voltage is not exceeded! is the second most significant bit. The switch control applies either the voltage Vm/2 or a zero voltage to the negative input of the subtractor, so that the subtractor subtracts the voltage from the doubled previous subtractor output.
The third most significant bit may be generated by repeating the process above, as may the fourth most significant bit. Each successive bit generated may be applied to an accumulator comprising a number of delay elements such as flip-flops. Such an accumulator can be used to present a digital representation of the analog signal value received. This can be accomplished by accumulating bits in delay elements, and then allowing the bits to be read out of these elements in the order of most significant bit to least significant bit.
There has been a considerable amount of interest in successive approximation type A/D converters, which interest is evidenced by and has lead to the developments discussed in a multitude of U.S. patents including U.S. Pat. No. 4,293,848 to Cheng et al., U.S. Pat. No. 4,647,903 to Ryu, U.S. Pat. No. 4,908,624 to Goto et al. , and U.S. Pat. No. 5,144,310 to Sato. A number of entities now manufacture such converters, and competition among those entities as well as a general scaling down of electronic apparatus in the recent past has created a great demand for relatively inexpensive converters with low power requirements.
Further, as time has passed, more and more uses have been found for successive approximation type converters. A large number of these uses involve telecommunications, wherein analog (e.g., voice) signals are now frequently converted to digital bit streams. A characteristic common to many of these uses is asynchronous requester behavior. Such behavior, frankly, has not been a primary focus of prior art successive approximation converters. Not surprisingly, therefore, the prior art lacks a successive approximation type converter well suited to handle asynchronous signals, configured so as to be easily manufactured, and designed so as to draw minimal power. The lack of such a converter is a shortcoming and deficiency of the prior art.